In conventional modern synthesis electronic design analysis (EDA) tools, a synchronous design is normally mapped to a set of gates (often standard cell gates), placed, and routed, all while meeting a large number of design constraints. Timing is normally at the top of the list of constraints. Without meeting the setup and hold time constraints, a design will not operate reliably under particular timing specifications. As a result, other design constraints, such as area and power, are often not efficiently improved by existing EDA solutions, since timing receives most of the focus in such systems. With scaling technologies often below a 100-nm minimum feature size, leakage power is becoming an increasing problem in modern integrated circuit (IC) designs. To mitigate the effects of subthreshold leakage current, most modern processes feature multi-threshold voltage (multi-Vt) standard cells. Low threshold (and subsequently high-speed) gates are used along timing critical paths. High threshold (and subsequently low-leakage) gates are used along non-critical paths. The ability to map a design to two or more sets of standard cells greatly complicates synthesis as an EDA tool attempts to meet timing while minimizing leakage current.
From a high-level, an optimally mapped multi-Vt design would be one that meets the specified timing constraints with zero positive timing slack while using the most efficient amount of high-Vt cells. Designs are often over-constrained to provide additional timing margins. A design with zero positive timing slack would be one that does not violate the additional over-constraint.
It would be desirable to implement a method that offers a near-optimal timing-leakage power balance.